1. Field of the Invention
The present invention relates to a semiconductor device on which a plurality of transistors are formed, and a method of manufacturing semiconductor devices. More particularly, it relates to a method of manufacturing semiconductor devices which is suitable when implementing a desired electronic circuit on a semiconductor substrate through the use of automatic layout and wiring means.
2. Description of the Prior Art
When categorizing available semiconductor device manufacturing methods broadly, there are two manufacturing methods for constructing a desired electronic circuit by using a semiconductor substrate on which a plurality of transistors are formed, and by connecting between the plurality of transistors according to wiring information.
One of them is the cell-based manufacturing method in which the circuit designer is required to not only design a desired electronic circuit according to some parameters of the semiconductor substrate, but determine the layout of transistors included in the electronic circuit. The other one is the gate-array manufacturing method in which the circuit designer is required to design a desired electronic circuit according to the transistor characteristics of the semiconductor substrate on which a number of transistors having the same size are arranged in the form of a two-dimensional array. The former cell-based manufacturing method has an advantage that it can offer a high-performance electronic circuit because the circuit designer can design the sizes and locations of the plurality of transistors included in the desired electronic circuit freely. The latter gate-array manufacturing method has an advantage that the circuit designer can design a desired semiconductor device by only doing the circuit design because the circuit designer does not need to design the plurality of transistors formed on the semiconductor substrate, and therefore can determine the locations of the plurality of transistors through the use of automatic layout and wiring means.
Another manufacturing method, which is called embedded-cell-array or ECA manufacturing method, capable of providing the circuit designer with general-purpose functional blocks such as macro cells including memories, A/D converters, and so on, is available now. The ECA manufacturing method is an improved version of the gate-array manufacturing method. Like the gate-array manufacturing method, the ECA manufacturing method offers an advantage that the circuit designer can design a desired semiconductor device through the use of automatic layout and wiring means. In addition, the ECA manufacturing method has another advantage that the circuit designer does not need to design functional blocks required by the semiconductor device because the circuit designer only selects a desired functional block from all functional blocks provided by the method and uses it as a part of the semiconductor device, resulting in a further reduction in the time required for the circuit design.
Referring now to FIG. 10, there is illustrated a plan view showing the layout of a semiconductor device which is manufactured by using the gate-array manufacturing method, as disclosed in "1995 Mitsubishi Semiconductor CMOS Gate Array 0.8 .mu.m Data Book". In the figure, reference numeral 1 denotes a transistor forming region in which a plurality of field-effect transistors are formed in the form of a two-dimensional array, 2 denotes a pointing pad for connecting an electronic circuit formed on the semiconductor substrate with an external pin, and 3 denotes an external input/output buffer located between an input/output transistor disposed within the transistor forming region 1 and a corresponding pointing pad 2, for interfacing between them.
Referring next to FIG. 11, there is illustrated a plan view showing an enlarged part of an example of the transistor forming region 1. In the example, both a plurality of P-channel field-effect transistors and a plurality of N-channel field-effect transistors are formed in the transistor forming region 1. In FIG. 1, reference numeral 7 denotes a P-channel diffusion area extending longitudinally in parallel with one side of the transistor forming region 1, 8 denotes an N-channel diffusion area extending longitudinally in parallel with a plurality of P-channel diffusion areas 7, 9 denotes a gate electrode. A plurality of gate electrodes 9 are arranged at predetermined intervals on each P-channel diffusion area 7 and on each N-channel diffusion area 8.
Referring next to FIG. 12, there is illustrated a plan view showing an example of the circuit layout of an electronic circuit which is formed in the transistor forming region 1 through the use of automatic layout and wiring means. In the figure, reference numeral 6 denotes a functional block, such as a logic circuit or a flip-flop, which constructs a part of the electronic circuit. Typically, through the use of automatic layout and wiring means, a gate-array semiconductor device can be configured so that a plurality of functional blocks 6 are arranged in each bank comprised of one pair of P-channel and N-channel diffusion areas 7 and 8 such that they are left-aligned, as shown in FIG. 12. Alternatively, a plurality of functional blocks 6 can be arranged in each bank comprised of one pair of P-channel and N-channel diffusion areas 7 and 8 so that they are right-aligned or aligned in another specified form.
Referring next to FIG. 13, there is illustrated a plan view showing the layout of a semiconductor device which is manufactured by using the ECA manufacturing method, as disclosed in "1995 Mitsubishi Semiconductor Embedded-Cell-Array/Cell-based IC Data Book". In the figure, reference numeral 10 denotes a general-purpose functional block such as a memory or an A/D converter which can be provided for the circuit designer. By using the ECA manufacturing method, a number of functional blocks are arranged in the transistor forming region 1 except a plurality of general-purpose functional blocks 10, so that a desired electronic circuit is constructed in the transistor forming region 1, like in the case of using the gate-array manufacturing method mentioned above.
While either of the prior art gate-array manufacturing method and the prior art ECA manufacturing method has advantages that the burden of design work the circuit has to do can be reduced, and the manufacturing time required to complete manufacturing one semiconductor device can be reduced, compared with the prior art cell-based manufacturing method, semiconductor devices manufactured by using either one of those prior art methods have disadvantages that a further improvement in the degree of integration cannot be expected and the power consumption in semiconductor devices manufactured is relatively large, compared with semiconductor devices manufactured by using the prior art cell-based semiconductor device manufacturing method.
To be more specific, using either the prior art gate-array manufacturing method or the prior art ECA manufacturing method, a number of transistors are formed in the transistor forming region so that all the transistors have a size which is large enough for all the transistors to operate as output buffers, because information on the uses of the plurality of transistors is unavailable. The size of transistors employed as the internal circuit of each functional block thus becomes larger needlessly. As a result, the size of each functional block is larger than that in the case of constructing a functional block having the same function by using the prior art cell-based manufacturing. This results in longer conductors installed in each functional block and hence a larger amount of capacitance that exists in each of the conductors.
In either one of the prior art gate-array manufacturing method and the prior art ECA manufacturing method, since a plurality of functional blocks are arranged on a semiconductor substrate through the use of automatic layout and wiring, some of all transistors formed in each bank are not used and therefore the utilization factor of transistors is reduced.
For the reasons mentioned above, the problems with both the prior art gate-array manufacturing method and the prior art ECA manufacturing method are that a further improvement in the degree of integration cannot be expected and the power consumption in semiconductor devices manufactured is relatively large, compared with the prior art cell-based semiconductor device manufacturing method.